Field of the Invention
The present invention relates to an information processing apparatus.
Description of the Related Art
There is a device having a circuit (also referred to as a configuration memory) provided with a plurality of logical blocks that can be programmed internally by a user. By a user programming each logical block, they can configure various logic circuits (corresponding to functions) on a chip. This programming refers to information of logic (for example AND logic or the like) realized by the logical block as configuration data, and is performed by writing to the configuration memory. This is referred to as configuration. As a representative device, a PLD (Programmable Logic Device) or an FPGA (Field Programmable Gate Array) may be given.
In recent years, a device that segments a configuration memory into a plurality of regions (also referred to as partial reconfiguration units), and enables configuration at separate timings for each partial reconfiguration unit has appeared. Such configuration is referred to as partial reconfiguration. Japanese Patent Laid-Open No. 2011-186981 discloses a method in which each of a plurality of logic circuits that comprise a pipeline are configured in corresponding partial reconfiguration units in the configuration memory in an order from the start of the pipeline.
In Japanese Patent Laid-Open No. 2011-186981, it is possible to configure by switching different logic circuits in one partial reconfiguration unit. In other words, if a plurality of partial reconfiguration units are present in a configuration memory, it is possible to configure a particular function (a logic circuit to realize a particular function) in a partial reconfiguration unit. When performing such a free-location partial reconfiguration, the following problems occur.
For example, a logic circuit corresponding to a function that an application program uses is configured in a partial reconfiguration unit of a device. The application program recognizes logical addresses of a plurality of registers that are accessed to control the logic circuit corresponding to that function. In other words, the application program recognizes a register space specific to the function. In contrast, even if a configured logic circuit is the same, the device allocates physical addresses of a plurality of registers accessed to control the logic circuit so as to be different for each partial reconfiguration unit. In other words, the device recognizes a register space specific to a partial reconfiguration unit. In such a case, if a logic circuit for a particular function is configured in an arbitrary partial reconfiguration unit, a register space recognized by a program that uses that function and a specific register space allocated to the partial reconfiguration unit in which the logic circuit of that function is configured will cease to match. As a result, by performing free-location partial reconfiguration of a logic circuit, an appropriate register of a partial reconfiguration unit from an address that an application program issues becomes inaccessible.